1. Field of the Invention
The present invention relates to computing systems, and more particularly to optimizing direct memory access (“DMA”) channel performance.
2. Background of the Invention
Storage area networks (“SANs”) are commonly used where plural memory storage devices are made available to various host computing systems. Data in a SAN is typically moved from plural host systems (that include computer systems, servers etc.) to the storage system through various controllers/adapters.
Host systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with storage systems via a host bus adapter (“HBA”, may also be referred to as a “controller” and/or “adapter”) using an interface, for example, the “PCI” bus interface. PCI stands for Peripheral Component Interconnect, a local bus standard that was developed by Intel Corporation®. The PCI standard is incorporated herein by reference in its entirety.
PCI-Express is another Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) that is compatible with existing PCI cards using the PCI bus. PCI-Express uses discrete logical layers to process inbound and outbound information. The logical layers are a Transaction Layer, a Data Link Layer (“DLL”) and a Physical Layer (“PHY”). PCI-Express uses separate links to transmit and receive information.
PCI-Express uses a packet-based protocol to exchange information between Transaction layers. Transactions are carried out using Requests and Completions.
The Transaction Layer assembles and disassembles Transaction Layer Packets (“TLPs”). TLPs are used to communicate transactions, such as read and write and other type of events.
Various other standard interfaces are also used to move data from host systems to storage devices. Fibre channel is one such standard. Fibre channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others.
DMA modules are used by HBAs to perform data transfers between memory locations, or between memory locations and an input/output port. DMA units provide address and bus control signals to and from a device for a read and/or write cycle.
A DMA read request is a request from a DMA module (or channel) to an arbitration module to transfer data from a host system to a storage device. A DMA write request is a request from a DMA module to an arbitration module to transfer data from the storage device to a host system.
Specific channels are implemented in a DMA unit to allow storage devices to transfer data directly to and from memory storage devices. A channel can be activated by a DMA request signal (DREQ) from a storage device or a host system. The DMA unit receives the DREQ, provides a DMA acknowledged signal (DACK), and transfers the data over the channel to or from the storage device.
HBAs typically use multiple DMA channels and have an arbitration module that arbitrates access to a PCI-Express link. This allows an HBA to arbitrate and switch contexts (between channels) by actively processing command, status and data. Multiple channels are serviced in periodic bursts.
Typically, DMA write requests may be processed by writing data using multiple PCI-Express write request packets. A new DMA request (read or write) can only be processed if a previous DMA read and/or DMA write request has been processed. DMA read requests (with no data) are issued to generate Read Transfer requests, which transfers data from the host to a storage device. Write requests from the storage device to a host system are generated using the same side of the PCI-Express interface. The same transmit link (in the PCI-Express interface) is shared for write transfers and read requests.
The time to service a write request can be longer compared to servicing the read request because write request packets (TLPs) also transfer payload data. Also, delay in issuing read request packets can stall data transfer from a host to a storage device.
Therefore, there is a need for a method and system to optimize DMA read and write request processing that allows both read and write data transfers to be conducted efficiently.